1. Field of the Invention
This invention relates to regulating the operations of a microprocessor by the use of one or more programmable logic arrays or gate arrays for filtering of certain commands to the microprocessor. More particularly, it relates to the use of programmable logic arrays or gate arrays for monitoring commands to a keyboard controller in a personal computer based on either the INTEL 80286 or 80386 microprocessor, and intercepting certain of those commands relating to the FORCE-A20 and CPU-RESET signals.
2. Description of the Related Art
In many popular personal computers based on the INTEL 80286 or 80386 microprocessor, there is a need for utilizing both real-address mode ("real mode") and protected mode. Real mode is used for initialization when first powered up, and mimicking of older 16-bit microprocessors, such as the INTEL 8086 family of microprocessors. In real mode, the 80286 or 80386 microprocessor uses segment and offset registers in the same way as the 8086 family to access the same one megabyte of memory. In real mode, the 16-bit instruction set, the segmented programming model, addressing mechanism, and one megabyte physical memory limitations are identical to those provided by the 8086. Thus the 80286 and 80386 microprocessors are compatible with the addressing scheme of the 8086 family.
In protected mode, the 80286 or 80386 microprocessor adds a series of features that allow it to safely and reliably expand the number of programs the computer can be working on at one time. This is accomplished through four main facilities: protection, extended memory, virtual memory, and multi-tasking. Protection allows the operating system to erect barriers to prevent a program from interfering with the operation of other programs or of the operating system itself. Extended memory greatly increases the amount of working memory beyond the 640 KB actually available to the software. Virtual memory allows the computer to go further beyond the installed physical memory limitations by shifting data to and from remote memory, such as hard disk. Finally, with multi-tasking supported by the hardware, the 80286 or 80386 can swiftly and reliably switch among several programs that are running at the same time.
A basic difference between protected mode and real mode is that the protected mode segment register is no longer a real (i.e., physical) address. Instead, in protected mode, the 80286 or 80386 uses the upper (most significant) 14 bits of the segment register to look up a 24-bit base address (with the 80286) or a 32-bit base address (with the 80386) stored in a descriptor table in memory.
Additionally, with protected mode, segment registers define the way that memory is organized between tasks. Each task has its own descriptor table describing the segments for that task. Since physical addresses are stored in the descriptor table rather than in the segment registers, the operating system can move memory around without application programs being affected.
Protected mode is so named because segments belonging to one task are protected from being corrupted by another task. Tasks are organized in privilege levels, and certain machine-code instructions are prohibited to lower privilege levels. In a well-designed protected mode operating system, a single program can neither crash the whole system nor get itself into an unrecoverable state.
Many personal computers based on the 80286 or 80386 microprocessors implement the "FORCE-A20" function. This function is necessary to maintain compatibility with software designed for systems based on the 8086 family of microprocessors.
The compatibility issue arises from the different memory address sizes available on the 8086, 80286, and 80386 chips. The 8086 had a one megabyte address range, with twenty address lines (A0-A19) driven by the microprocessor. The total range was 2 raised to the 20th power, or 1,048,576 possible addresses (one megabyte). In contrast, the 80286 has 24 address lines, giving 16 megabytes of address range (2 raised to the 24th power); the 80386 has 32 address lines, giving 4096 megabytes of address range (2 raised to the 32nd power).
The 8086 microprocessor uses a segmented memory addressing scheme. The effect of this scheme is to allow a software program to access only a 64 KB "window" out of the one megabyte total range. To access memory outside this window, the window's location must change, and this operation takes time.
To access memory near the top of the one megabyte address space as well as memory near the bottom of the 8086's one megabyte address space, without moving the window, some software takes advantage of "memory wraparound". This feature on the 8086 may be used when the base of the 64 KB window is less than 64 KB from the top of the one megabyte address range, so the top of the window would extend beyond the highest possible address location. When the window is in such a position, these impossibly high addresses are simply "wrapped around" to low addresses, much in the same way that an odometer goes from 99,999 to 00,000 miles. Thus, software could access very high as well as very low addresses in the same window.
Since the 80286 and 80386 microprocessors have more than one megabyte of address range, these microprocessors do not wrap around memory addresses at one megabyte. Instead, accesses to the part of the window above one megabyte are put out as actual addresses greater than one megabyte.
The difference between the old 8086 "wrapped around" low addresses and the new 80286/80386 high addresses is that the new 80286/80386 microprocessors have extra address lines beyond A19 (much like having extra digits on an odometer, so it doesn't wrap around after 99,999 miles). The first of these address lines on the 80286 or 80386 is A20, and it is set high for all addresses in the range from one megabyte to two megabytes (in the absence of the FORCE-A20 command). The A20 line is set low for addresses below one megabyte.
In real mode, the 80286 and 80386 microprocessors behave as much as possible like the 8086 microprocessors. Thus, in real mode the 80286 and 80386 cannot access memory above one megabyte. Because the 80286 or 80386 have more than one megabyte address range, the wrap-around feature of the 8086 family of microprocessors does not work on the 80286 or 80386 (in real mode) unless the A20 line is low. When the A20 line is low, the 80286 or 80386 can simulate the wrap-around feature.
To allow software with wrap-around windows to operate on the 80286 or 80386 microprocessors, the prior art has employed various techniques to intercept the A20 line from the microprocessor and force it low. Forcing the A20 line low makes addresses put out by the microprocessor in the range of between one and two megabytes result in an address one megabyte lower. The signal that causes the A20 line to stay low is called "FORCE-A20".
When the 80286 or 80386 microprocessor returns from real mode back to protected mode, the FORCE-A20 signal must be turned off, so that the software has the ability to use the full address range (beyond one megabyte) available to the microprocessor.
The FORCE-A20 signal does not actually cause the microprocessor to switch between protected and real mode. The actual switching of modes is accomplished either by executing special instructions in the microprocessor or by resetting the microprocessor. Setting the FORCE-A20 signal is simply something that must be done by the software program to insure the wrap-around feature will not prevent proper functioning of the program.
In the prior art, the FORCE-A20 signal was controlled by an extra output pin on the 8042 keyboard controller. This prior art solution was chosen because the extra output pin was not otherwise needed, and because at the time nobody foresaw any need to switch between real and protected mode more than occasionally. The problem, however, of putting the FORCE-A20 signal under the control of the 8042 keyboard controller was that access to the signal was possible only by sending a command to the 8042, which then executed a routine to alter the state of the output pin. This process typically takes approximately 200 microseconds. The delay was found to be undesirable in many applications.
Many of the protected mode software programs utilizing the 80286 or 80386 microprocessors must disable the FORCE-A20 signal before switching to protected mode, and then enable it after returning to real mode. The prior art has controlled the FORCE-A20 signal by sending commands to the 8042 keyboard controller. Some of the newer software has needed to switch between protected and real mode very frequently, so that the delay for switching (approximately 200 microseconds) caused by the 8042 keyboard controller became a significant part of the program's execution time.
The present invention solves the delay problem resulting from utilizing the 8042 to control the FORCE-A20 signal, so that all existing software that calls on the 8042 to change the FORCE-A20 signal is not obsolete and the delay caused by the 8042 is reduced substantially.
The prior art has attempted to solve this delay problem by installing an additional, separate hardware port for the FORCE-A20 signals. This attempted solution, however, is incompatible with much of the existing software which utilizes the existing port on the 8042. Therefore, a need exists for implementing the FORCE-A20 command without delay by the 8042 keyboard controller, in a system compatible with existing software.
Many personal computers based on the 80286 or 80386 microprocessors also implement the "RESET-CPU" function. The RESET-CPU command activates the RESET-CPU signal, which addresses the 80286 or 80386 microprocessor reset input. When the signal is activated, it causes the microprocessor to stop whatever it is doing and start its initialization sequence.
One use for the RESET-CPU command is to switch from protected mode to real mode in a system based on the 80286. When the 80286 microprocessor is reset, it defaults to real mode. The RESET-CPU command, however, is not generally used by application software because it may cause the system to reboot. The system does provide that control can be returned to a program already residing in memory even after the CPU has been reset. Thus, if a protected mode program wishes to switch to real mode on an 80286 microprocessor, the program must reset the CPU, then regain control after the reset occurs.
It should be noted that the 80386 microprocessor, unlike the 80286, provides a specific instruction to switch from protected to real mode. However, software developed for the 80286 does not utilize this 80386-specific instruction.
If a software program switches from protected to real mode frequently, then it must reset the CPU frequently. The RESET function is a strobe or pulse typically controlled by the 8042 keyboard controller. In the prior art, the command to change the CPU-RESET signal has utilized yet another extra pin on the 8042, just as the FORCE-A20 signal utilized an extra pin. In the prior art, the 8042 RESET-CPU command holds that signal active for a short period of time; i.e., about five microseconds. The RESET-CPU signal resets the CPU, and then allows it to restart. However, since the 8042 hardware controls this function, the software program must wait for the relatively slow 8042 to respond during every RESET. Because the signal utilizes an extra pin on the 8042, there is typically a delay of approximately 200 microseconds for the 8042 to respond to the command., i.e., from the time that the CPU-RESET strobe command is sent to the 8042 until the time the 8042 starts the strobe. This additional 200 microsecond delay was found to be undesirable in many applications.
Attempted solutions to this delay problem include installing an additional, separate hardware port for the CPU-RESET signal, but this attempted solution is incompatible with much of the existing software. Another alternative method is to cause a CPU-RESET from software without using the 8042. This alternative is called a "triple fault". The triple fault is done by intentionally causing an execution error while in protected mode. When this happens, the CPU will automatically begin executing an error handling routine. If there is also an error in the first routine, the CPU goes to a second error handling routine. If there is an error in the second error handling routine, the CPU resets itself. Although this triple fault sequence is faster than the 8042 hardware reset, this approach has not been utilized by existing software applications. Therefore, the need exists for implementing the CPU-RESET signal, compatible with existing software and without delay inherent in the 8042 keyboard controller.